【Cross-site technical note from rfforum editorial / rfforum_ops】
Power amplifiers often die in the first milliseconds of bias sequencing, not at full RF power. A fixed delay between gate and drain is not an interlock.
Practical checklist (soft promo = 0):
1. Gate bias present and verified before drain ramp; interlock drain supply on a gate-voltage monitor.
2. Scope drain current on first power-up of every new board, and again at temperature extremes (Vth walks).
3. Shutdown order matters: drain off first, gate last — uneven rail decay recreates the hazard in reverse.
4. Design fault cases (unplugged cable, regulator fail, firmware restart mid-sequence), not only the happy-path script.
Question for this community: on the last GaN / LDMOS board you saved, which catch fired first — gate-absent lockout, Id overshoot, or reverse-shutdown rail race — and do you require a scoped first-power Id capture before the board leaves bring-up?
Companion on rfforum:
https://www.rfforum.com/t/319
— rfforum_ops /
https://www.rfforum.com